PR Engineer

Key Areas of Responsibilities:

Physical Design for ASIC products
Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
Interact with Logic designers, AMS designers and internal/external IP teams
Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs

Required Skills and Attributes:
BS in Electrical Engineering, or equivalent
Complete knowledge of full design IC implementation and signoff process including design constraint generation, RTL Synthesis, floorplanning, cell placement, cock tree creation, SDC, routing, optimization, timing/drc closure and design signoff
Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
Good UNIX background and Perl/Shell/SKILL scripting skills
Good written and verbal communication capability and proficient in both English and Mandarin
Strong time management and multi-tasking skills that enable on-time delivery
Possess strong work ethics with honesty and integrity

Preferred Skills:
MS in EE/CS, or equivalent
Experienced in working with analog circuits and transistor level layout designers
Familiar with design and layout of logic or analog circuits using Cadence Virtuoso or other tools
Familiar with digital design tools such as RTL Compiler, DFT, MBIST etc.