（DFT）DFX工程师/可测性设计工程师

DFT 需要不断进化和创新来应对新工艺新需求，目前，DFT 已经转变为多维度的 DFX，关于什么是 DFX, 一个公式告诉你：
DFX = DFT+DFM+DFR+DFD+……
DFT：Design for Testability
DFM: Design for Manufacturability
DFR: Design for Reliability
DFD: Design for Debug

在 NVIDIA DFX 团队，聚集着来自全球各地的专家及优秀人才，若想体验全球化的团队协作，这里一定是不二之选。在这里，你可以抢先见证最前沿且持续创新的 DFT / DFX 技术。这里有强大的设计和验证平台，为一次流片成功提供强有力的支持。除此之外，NVIDIA DFX 团队拥有开放的企业文化，同时还为团队成员提供了更多的职业发展机会。

目前，NVIDIA 上海 DFX 团队已拥有各个领域的技术专家，具备独立完成芯片 DFT 设计和实现的能力，在全球团队中引领 DFT 的设计验证工作。该团队在上海设有 ATE lab 和 ATE 测试机台，可以第一时间解决芯片生产初期 bringup 的问题，从而实现为芯片量产加速。

你将参与 GPU 和 Tegra 产品线的研发，与 SOC、PD、PR 等团队配合，完成 DFT 从 RTL 到 tape out 的芯片实现工作；与 TE、PE 等团队合作，完成芯片 ATE bringup 工作。

未来，你将负责以下一项或多项具体工作内容：
• JTAG 1500 / 1687
• DFT Clock
• DFT Insertion
• ATPG
• BIST (MBIST, LBIST, etc.)
• IST and Online Test
• ATE Bringup
• DFT Design / Methodology
• DFT Infrastructure / Flow Development

【我们期待这样的你】
• 了解 DFT 的主要技术，具备 Scan / ATPG / BIST / JTAG / Clocks / Bringup 等任一方向工作经验（对 NCG 或 Intern 可不做要求）
• 熟悉 Tcl、Perl、Python 等脚本语言
• 有数字芯片前端或后端设计经验为加分项
• 良好的英语读写和口语交流能力
• 敢于接受挑战，富有创新精神

JD
We are now looking for a DFT Engineer.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people.

Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

What you'll be doing:

DFT planning, implementation, verification and silicon bring up at IP or fullchip level for all of NVIDIA's semiconductor products.

Take lead role of some DFT areas in a project.

Improve DFT design, architecture and flow.

What we need to see:

Familiar with Verilog and ASIC design.

Proven knowledge and expertise in JTAG, Scan, BIST including memories and IOs, ATPG, fault models and fault simulation, etc.

Excellent analytical skills in verification and validation of test patterns and logic on sophisticated VLSI designs.

Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.

Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics.

Strong programming and scripting skills in Perl, Python or Tcl desired.

Outstanding written and oral communication skills in English with the curiosity to work on rare challenges.