数字后端设计工程师

VLSI Physical Design 部门成立于 2005 年， 在过去的 16 年里，我们成功地参与并设计了 NVIDIA 发布的所有产品。我们使用了前沿领先的生产工艺、EDA 工具以及最复杂的设计流程。致力于先进的产品设计，挑战技术之巅是我们一贯的追求。

【未来，你将在这些方面施展才华】
负责 NVIDIA 公司所有芯片（包括 GeForce，Tegra，Tesla，Quadro 等系列）的物理设计及其实现（Netlist to GDSII）， 以及流程开发（Flow development）。
致力于：
-芯片规划及布局, 顶层设计到底层模块的划分
-电源 / 时钟分布及规划
-布局布线 (包含从顶层设计以及底层模块的全部内容)
-静态时序 / 功耗 / 噪声 / 可制造性优化及分析
-物理验证
-流程自动化以及回归测试
-与 EDA 提供商合作进行工具评估和改进
-开发内部工具和解决方案

【我们期待这样的你】
-有数字芯片后端设计相关工作经验
-有 EDA 工具使用经验 Synopsys （ICC2 / DC / PT / STAR - RC), Cadence (EDI / Innovus/ Voltus) or Ansys (Redhawk)
-有如下工作经验 Floorplanning, P&R, Timing closure, Power / Clock analysis
-有芯片物理验证相关经验
-有使用 Perl，Tcl，Python 和 Shell 等语言编写脚本的能力优先

Job Description
We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.

What you’ll be doing:
A senior role in physical design for NVIDIA GPU and Mobile chips Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see: 
• BS in Engineering or Science or equivalent experience.
• Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC),Cadence (EDI/Innovus/Voltus) or Mentor (Olympus-SOC).
• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.
Ways to stand out from the crowd: 
• MS in Engineering or Science.
• Knowledge in FinFET technology, circuit design, and package design.
• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).
• Proficiency in Perl, Python, TCL and Makefile scripts.