资深IC设计工程师 (深度学习硬件加速) Senior ASIC Design Engineer (NVDLA (Deep Learning Accelerate))

薪资待遇面议

工作职责
1. Building next generation of NVDLA for both internal usage and open source
2. Co-work with architect to define NVDLA’s architecture/micro-architecture
3. Full design flow on NVDLA hardware modules
4. Support for verification/validation process

任职资格
1. BS/MS in electrical/computer engineering and related.
2. 3+ years’experience in ASIC IP design. 
3. Strong digital design skills including Coding/Debugging/Micro-architecture. 
4. Solid understanding in timing/power optimization.

加分项
1. CPU/GPU design experience, or deep-learning/image processing experience
2. Good understanding on Deep-Learning algorithm/application is a plus
3. C/C++ skill, scripting skill.
4. Fluent English (both written and spoken) and excellent communication skills
5. Demonstrated ability to work independently as well as in a multi-disciplinary group environment