ASIC Verification Engineer

ASIC Verification Engineer
Responsibilities
1. Work with Architecture, Design and Software team to ensure micro-architecture and design is fully verified
2. Contribute to verification infrastructure development
3. Modeling of design modules/interfaces
4. Test plan execution based on functional requirements, drive coverage closure.
5. Real work location is not confined to Shanghai
Skill requirement
1. >1 year hands-on experience in ASIC/FPGA design verification.
2. Master’s degree desired, Bachelor's degree in CS/EE is required.
3. Should have worked on design verification at block/chip-level for complex ASICs.
4. Fluent in System Verilog/C++, script languages such as Python or Perl.
5. Have knowledge of UVM methodology.
6. Experience with code coverage, formal verification tools; familiar with evolving verification methodologies.
7. Experience in the verification of network chip is a big plus.
8. Experience in the verification of SoC and other IPs listed below is a plus: 
High Speed SerDes, PCIE, CPU Subsystem, Ethernet.
9. Highly motivated, positive, detail oriented and responsible
10. Good team player and good communication skills

Contact Info
If you are interested, please send your resume to wangxiujuan@clounix.com
​HR 联系电话：13757103066