- 4万-8万/年
- 北京
- |
- 应届生/在校生
- |
- 本科
- |
- 实习
职位诱惑: 老板nice,技能培训,成长空间大,技术领先
发布时间: 2020-02-28发布
职位描述
数字后端实习生PD and Power Reductions Intern
Key Responsibilities
1. Power reduction Methodology in Digital physical design
2. Floorplan, Place and Route , Timing/DRC/IR/EM checking/fixing
3. flows/tools methodology
Skills and Experience Requirements
1. Understanding basic ASIC design flow
2. Bachelor and above in microelectronics, or related area
3. With experience on Verilog or System Verilog
4. Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus
5. Nice to have development experience under Linux, knowledge of Shell/Make/VIM/
LOCATION:
Beijing
职位发布者
AMD
HR
7天
简历处理用时
100%
简历及时处理率
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