- 30万-60万/年
- 北京
- |
- 3年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,成长空间大,技能培训,技术领先
发布时间: 2020-04-22发布
职位描述
Responsibilities:
- Responsible for DFT planning regarding to IP or SoC
- Responsible for implementation and verification for MBIST
- Responsible for implementation and verification for Scan/ATPG
- Responsible for DFT pattern generation, release and ATE bring-up
- Responsible for DFT flow/quality improvements
Requirement:
- Major in CS, EE or related, BSEE required, MSEE preferred
- 2~10 years of hands-on experience in DFT related field
- Strong knowledge of DFT including scan, ATPG, BIST and other DFT methodology
- Strong experience with popular DFT EDA, Mentor DFT solution is preferred
- Knowledge of synthesis, STA is a plus
- Familiar with common UNIX utility such as Shell, Perl, TCL
- Good English communication skills
- Self-motivated and good team player
职位发布者
王晓丽
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