PMTS Design Verification Engineer

Responsibilities
• Work closely with the other members of the Radeon Technology Group Hardware IP technical management team to provide leadership and set goals and directions for the development of the next generation of graphics processing intellectual property and verification flow.
• Provide technical leadership to low power Graphic IP verification teams, which are responsible for block architecture review, software modeling, netlist integration, and verification. Have a strong emphasis on expertise in one or more GFX-IP blocks or IP level knowledge.
• Provide first level technical management for GFX-IP blocks or GC level, example like ALU data path (SP) or Sequence (SQ), other GFX-IP blocks or DV/PV expertise to work with execution team.
• Provide direct individual contributions as needed to ensure projects are completed on time and with high quality.  Actively support our continuous verification process improvement projects.
• Provide Technical task management for one or more GFX-IP GC level or Block level .
 
Requirements:
• BSEE/MSEE Electrical Engineering or Computer Engineering; MSEE or MSCE preferred.
• 10+ years of Graphic IP development experience including familiarity with the entire ASIC development process and tools
• 10 years engineering experience with a history of leading the development of successful high technology products
• Keen understanding of Graphic and System Level issues & requirements
• Solid Verilog or VHDL and C/C++ and scripting skills
• Solid RTL Design, Validation, and Synthesis experience
• Full Chip Validation and debug experience in ASIC’s or large FPGA’s
• Strong interpersonal skills that enables successful interaction with a large worldwide team
• Patents, paper, or awards are a plus