- 20万-30万/年
- 上海
- |
- 1-3年
- |
- 本科
- |
- 全职
职位诱惑: 成长空间大,十五薪,福利好,技术领先
发布时间: 2020-04-02发布
职位描述
JOB DESCRIPTION:
1. Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow
2. Do SoC/IP level synthesis / timing analysis / formality check / CDC check
3. Deliver constraints and closely co-work timing closure with P&R
4. Take some block level RTL coding
QUALIFICATION:
1. MSEE with ＞3 year+ experience of digital design experience;
2. Relevant experience in complex timing closure;
3. Be familiar with DC/PT/formality check tools
4. Be familiar with Tcl/Perl/…. Scripts language
5. RTL coding experience is a plus
职位发布者
Roger Tang 汤冯喆
Recruitment Expert
7天
简历处理用时
100%
简历及时处理率
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