SMTS Design Verification Engineer

RESPONSIBILITIES:
·        Overseas definition, design, verification, and documentation for ASIC development
·        Contributes to verification infrastructure setup
·        Determines architecture design, logic design, and system simulation
·        Defines module interfaces/formats for simulation
·        Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results
·        May also review vendor capability to support development

REQUIREMENTS:
·        Familiar with Verilog HDL coding and ASIC Frond-End implementation flow
·        Computer architecture and computer arithmetic
·        Computer graphics basic knowledge
·        Strong UVM/C++ knowledge
·        Experience with database technologies and database-driven custom web application development
·        Familiar with Unix/Linux and scripts (TCL, Ruby, Perl, Python etc.)
·        Strong problem-solving skills, and attention to details
·        Strong task-based organization skills
·        Good interpersonal skills (verbal and written)
·        Strong passion in achievement and career development
·        A self-motivated team player

EDUCATION:
·        Masters in CS/EE with relevant course work and project background with 10+ years of experience