Block level PD engineer

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30万-40万/年
成都
|
5年以上
|
本科
|
全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2022-11-10发布

职位描述

岗位职责:
1. Implements block level physical design, including floorplan, placement, CTS , routing, parasitic extraction, STA, Power analysis, Xtalk analysis, physical verification and ECO.
2. Solves block level timing, congestion, and IR/EM issues
3. Work with full chip engineers to achieve timing closure for both partition and full chip level

任职资格:
1. Bachelor or Master Degree in Engineering (Microelectronics, Electronics)
2. 2+ years of hands on experience in large scale ASIC chip physical design
3. Experienced with common EDA tools flow, ie: ICC/Innovus/Prime Time/Calibre
4. Successful tape out experience is a plus
5. Good teamwork and communication skills
6. Familiar with scripting/programming (TCL, Perl, shell script, C)
7. Language: Good English read/write