- 26万-50万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,股票期权,天天下午茶,年度旅游,交通补助,技能培训
发布时间: 2020-02-11发布
职位描述
Responsibilities：
1. Responsible for the design physical implementation from netlist to GDS tape out, including:
2. Chip/Block floorplan;
3. CTS, Power plan, Placement & Routing, SPF extraction;
4. DRC/LVS, and GDS tape out.
Requirements:
1. 2-5 years of experience and minimum of BS in EE or equivalent; MS a plus. Experienced in one of the major P&R (Place & Route) tool suites (Cadence, Synopsys);
2. Background in timing closure and signoff (PrimeTime experience);
3. Scripting expertise (Perl, Tcl, or Python) a strong plus;
4. Actual chip tapeout experience on a recent technology node (40nm or below) a strong plus.
更多地平线愿景可戳Bloomberg Markets: China Open 采访：https://mp.weixin.qq.com/s/4DtSP1rfqByShkuPQ0o_-g
职位发布者
李莉萍
HR
7天
简历处理用时
100%
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