- 25万-45万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,通讯津贴,福利好,年底双薪,股票期权,天天下午茶,免费班车,技能培训
发布时间: 2019-03-05发布
职位描述
1.Develop and support FPGA design for SOC development
2.Responsible for FPGA RTL coding, and migration between ASIC database and FPGA database
3.Responsible for FPGA synthesis/PR timing clean-up and bit file generation
4.Responsible for system-level work and FPGA debug with signal probe tools
Requirements:
1.Bachelor or above degrees in EE/Communication/CS majors with >= 3 years related working experience
2.Must have experiences in digital logic design with Verilog/VHDL...etc.
3.Must have experiences with Xilinx Virtex/Spartan products and familiar with FPGA synthesis flows and tools (ISE, Vivado, Synplify, Chipscope, Protolink…etc)
4.Experience with DDR/ARM/USB FPGA design is a plus.
5.Experience with Synopsys HAPS or equivalent prototype systems is a plus.
职位发布者
秦遇蛇
Sr.Consultant
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