ASIC Design Engineer

收藏职位

32万-48万/年
北京
|
5年以上
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,技能培训,成长空间大,技术领先

发布时间: 2022-11-10发布

职位描述

岗位职责:
1. SOC front-end design, including clock, reset, system control, top interface
2. Responsible for RTL quality and module level synthesis
3. Support DV for function verification
4. Support software driver development

任职资格:
1. minimum 3+/6+ years of ASIC design,
2. Proficient in Verilog HDL, knowledge of system architecture and design
3. Solid working experience with Arm architecture and AMBA
4. Familiar with front-end design flow and EDA tools
5. Strong problem solving, communication skills and good team work spirit
6. solid knowledge in one of the following area:
 DDR/HBM Memory controller
 PCIE design
 GFX design