Senior Digital IC Design/Verification Engineer

职位诱惑: 五险一金,福利好,老板nice,技术领先,成长空间大,技能培训

发布时间: 2019-06-28发布

Description

As a team member to design and verification next-generation Mixed-Signal Communication SoC
Digital IC design from RTL to netlist including synthesis, timing constraint composing, DFT, ECO
Digital IC design including synthesis, verification, algorithm implementation, etc.
Program development in TCL/Python/... to improve productivity

Qualifications

BS/MS in ME, EE or CS.
Positive, active, self-motivated and teamwork
2+ years of hands-on experience in IC design industry
Experiences on Cadence, Synopsys, Mentor EDA tools
Real tape-out experience is a good plus
Familiar with UVM verification methodology is a plus
Experiences on verification on FPGA and familiar with FPGA EDA tools is a plus
Familiar with HW/SW interface, any CPU ISA like RISC-V/ARM/MIPS/... is a plus
Network/Communication System/DSP/Mixed-Signal/Automotive design experience is a plus