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景略半导体
Digital IC Design/Verification Engineer (junior)
收藏职位
- 10万-20万/年
- 上海
- |
- 应届生/在校生
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,老板nice,技术领先,成长空间大,技能培训
发布时间: 2019-06-28发布
职位描述
Description
- As a team member to design and verification next-generation Mixed-Signal Communication SoC
- Digital IC design including synthesis, verification, algorithm implementation, etc.
- Program development in TCL or other script language to improve productivity
- BS in ME, EE or CS.
- Positive, active, self-motivated and teamwork
- Real project experiences in college is a plus
- Experiences on Cadence, Synopsys, Mentor EDA tools is a plus
- Experiences on verification on FPGA and familiar with FPGA EDA tools is a plus
职位发布者
郭雄飞
设计总监
7天
简历处理用时
100%