Synthesis and Signoff Engineer

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25万-50万/年
上海
|
工作经验不限
|
本科
|
全职

职位诱惑: 股票期权,年终奖金,技术领先,成长空间大,五险一金,福利好,老板nice,节日礼物

发布时间: 2019-05-17发布

职位描述

Job Description
·        Responsible for block /full-chip MCMM physical aware synthesis
·        Co-work with physical design team to drive the best PPA
·        Responsible for SDC finalizing
·        Responsible for timing ECO and signoff
·        Responsible for UPF writing and VCLP low power signoff
·        Responsible for formal verification
·        Responsible for power evaluation
·        Be a highly-valued member through excellent collaboration and teamwork with other teams
Qualifications
·        BS degree or higher in EE, CE, or CS
·        2+ years hands-on experience as DFT/Synthesis/STA engineers
·        Strong SDC writing and debugging experience
·        Strong physical aware synthesis experience
·        Strong timing ECO and STA signoff experience
·        Strong Formal verification experience
·        Good knowledge to UPF and low power check
·        Strong debugging and analytical skills
·        English documents reading
·        Good programming in Perl/Python, TCL and Shell programming
Self-motivated, team work, and good communication skills