ASIC Design/Verification Engineer 设计验证工程师

Job Description
·        Analog and digital IP integration for SoC and verification
·        RTL handoff quality check using EDA tools
·        Prepare relevant SDC file
·        Prepare relevant UPF file
·        Co-work and Support ASIC implementation
·        Co-work and Support FPGA prototyping
·        Co-work and Support software and system productions
·        Write design documents
Qualifications
·        2+ years hands-on experience in ASIC RTL design. Experience in Bluetooth, Mobile Computing or IoT is a plus
·        ASIC design verification and implementation knowledge
·        Good knowledge to RTL QA tools (for example Spyglass)
·        Good knowledge to UPF and low power verification (for example VCLP and VCS-NLP)
·        English documents reading
·        Good programming in Perl/Python, TCL and Shell programming
·        Good team work and communication skills
Location
      Room 310, No.500, Bibo Road, Pudong, Shanghai