数字前端验证 Design Verification Engineer

RESPONSIBILITIES:

• Oversees definition, design, verification, and documentation for ASIC development.
• Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.
• Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
• Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.
• Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

• Experience in power targets, IP selection, floorplan review etc.
• Develop RTL code for chip level in Verilog HDL and make sure functional correct and reusable for different configuration.
• Synthesis Participate in SOC IC project logic design
• Working with architect to define chip level specification, including clock and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
• Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
• Bring-up ASIC.
• Guide hardware team to solve design problem in application.
• Help to short Time-To-Market.
• Is required to undertake high-level technical assignments with strategic impact.
• Synthesizes marketing requirement, technology and implementation.
• Contributes to the development of product strategy and provides technical leadership in the development of new products, processes or technologies in support of this strategy.
• Represents the key technology resource to a large engineering team or group.
• Contributes technology leadership for multiple projects and collaborates with marketing to develop the right technology and business choices.
• Typically contributes across projects within product groups or technology development initiatives.
• Provides technical leadership; may have limited management accountability for a small number of engineers related to projects, (e.g., interview and selection, day-to-day technical supervision or mentoring)

• BS + 5 years or MS 3 years+ or PhD 2yrs+
• Generates publication(s) relevant to areas of expertise