Design Verification Engineer
- 25万-40万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice
发布时间: 2019-02-27发布
职位描述
RESPONSIBILITIES:
IOHUB/IOHC/IOMMU IP verification:
Develop Test Plan and new test cases;
Develop function coverage points;
Maintain regression;
Global team co-work;
REQUIREMENTS:
• 5 years’ + for Master or 8 years’ + for Bachelor work experience
• Design Verification experience in C++/UVM for IP or SoC chip level
• ASIC Verification with knowledge of System Verilog , Verilog, script language, like: perl, shell
• Know architecture of X86 /ARM system is a plus
• Have PCIE/AXI bus experience is better
• Knowledge of Unix and Linux is highly desired
• Strong verbal and written communication skills in English
• Strong teamwork skills with good human relationship