MTS/SMTS ASIC/ Layout Design Engineer

Job Summary:
NBIO Silicon Support Team (SST) engineer team is seeking an experienced engineer to lead the IP bring up and validation for PCIe/PCS. which include feature enablement and optimization, issue debug, and customer support.
Job Responsibilities:

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

AMD NBIO (North Bridge IO) team delivers industry leading high performance interconnects IP subsystem for all AMD products including discrete GPU, Machine Intelligence, APU, Server and Game consoles. You'll be working with the global team as NBIO SST member
Responsibility:
• SST engineer will be key person to drive PCIe/PCS and NBIO/DXIO related IP to validation and bring-up.
• Work closely with IP design team to define IP validation test plan for both pre-silicon (emulation) and post-silicon
• Lead ASIC/ IP feature bring-up and validation, ensure coverage and schedule will meet Ax/Bx tape-out date
• Drive cross-team (ASIC design, platform, driver) collaboration to enable IP features and optimize performance
• Lead related engineering teams(global) to debug related issues for the IP
• Work with characterization team to figure out the optimize for the IP
Job Requirements:
Education& Qualifications:

1. Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC front end work background
Experience:
1. A minimum of 5+ years' experience on low level FW/SW development or ASIC design verification
2. Strong leadership for issue debug and program driving
3. Strong debugging and testing skills
4. Expert in PCIe Protocol
5. Familiar with Linux/Windows PCIe debug, experience with logic analyzer and PCIe protocol card
6. Hands-on experience with any one of ASIC bring up, power management, PCIe, Ethernet is preferred
7. Strong communication skills
8. Good English required - verbal and written
9. Familiar with firmware development and debug
10. Familiar with schematic / PCB layout