layout

收藏职位

10万-15万/年
上海
|
1-3年
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,福利好,技能培训,技术领先,成长空间大

发布时间: 2019-01-02发布

职位描述

1. BS and above in Electrical or Related Areas.
2. Good understanding of advanced semiconductor technology process and device physics.
3. Fullcustom circuit layout/verification and RC extraction experience. Experiences in one or
more of the following area is preferable:
● Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.
● High performance/capacity memory layout, e.g. SRAM, RF, RA, etc.
4. Familiar with Cadence Virtuoso environment and various industry physical verification tools
(DRC,LVS,DFM, etc).
5. Experiences in advanced technology node under 32nm/28nm/16nm/14nm and FinFET is
preferable.
6. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable.
7. Good English skills, communication skills, and willingness to work with a global team.
8. Good learning competency, selfmotivated, and ability to work in diverse areas in a flexible
and dynamic environment.