Senior Analog Design Engineer

GENERAL SUMMARY:
 
We are seeking for Senior Analog Integrated Circuit Designers with excellent design skills who will be contributing in a team environment in the development of high-speed mixed-signal IPs in advanced CMOS processes. You will use your skills as an Integrated Circuit designer while applying them to a vast array of process technologies, system applications, and new technology development. Tasks will include the development of block level definitions and requirements, detailed circuit design and schematic creation, circuit simulation, manual layout, physical verification (Layout vs. Schematic and Design Rule Checking), behavior modelling using Verilog-A or Verilog-AMS, and full chip verification in a variety of silicon process technologies.
 
PRINCIPAL DUTIES AND RESPONSIBILITIES:
 
- Design automatic skills in IC custom design tools (e.g. Cadence or Mentor) for
schematic capture, circuit simulation, full custom layout; mixed-signal circuit design;
- Physical verification skills;
- Behavior modelling skills;
- Using Verilog-A or Verilog-AMS, and full-chip functional/performance verification
methods.
 
REQUIRED COMPETENCIES:
 
- Tape out experience of following area: high speed and high-resolution ADC/DAC/VGA (variable gain amplifier), high speed SERDES, high-performance VCO/PLL, LDO, etc.
- Familiarity with sub-threshold designs, familiar with 55nm/28nm/14nm CMOS process;
- Excellent understanding of device physics
- Experience performing chip level integration
- Experience in electronics test lab
- Self-motivated with good analytical and problem-solving skills. Excellent communication and teamwork skills.
 
MINIMUM QUALIFICATIONS:
Advanced degree -either MS or PhD in Electrical Engineering with proven record in
analog and mixed signal design experience.
 
PREFERRED QUALIFICATIONS:
- 2+ years with a technical MS on analog circuit design, simulation, layout guidance,
chip tests;
- 1+ years with a technical PhD on analog circuit design, simulation, layout guidance,
chip tests;