数字前端设计工程师

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25万-35万/年
上海
|
3年以上
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间: 2021-09-13发布

职位描述

This position is for IP design and synthesis
Work as synthesis owner, maintain IP synthesis environment
Maintain synthesis regression with different configurations
Create floorplan and run DCT flow
Figure out critical paths and debug with RTL designers
Run synthesis with customer's configuration, support customer for synthesis and timing issue

Typically requires a minimum of 4 years of related experience
Has strong desire to learn and explore new technologies
Demonstrates good analysis and problem-solving skills
Experience in RTL design is a plus
Experience in backend design is a plus
Knowledge in DDR and interface technologies such as PCIe, USB is a plus