- 19万-30万/年
- 南京
- |
- 1-3年
- |
- 本科
- |
- 全职
职位诱惑: 技术领先,成长空间大,年终奖金,五险一金,年度旅游
发布时间: 2018-08-13发布
职位描述
1. The candidates should have BS or MS in Electrical Engineering or related.
2. The candidates should have 1~5 years of experience in front-end ASIC design, mainly in Verilog RTL coding, linting and assertion based formal verification.
3. Experience with TCAM/Networking/Storage is a plus.
4. Experience with synthesis and STA is a plus.
5. FPGA emulation experience a plus.
6. Good communication and problem solving skills.
职位发布者
芯启源（南京）半导体科技有限公司
HR
7天
简历处理用时
100%
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