ASIC Layout Design Engineer

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30万-40万/年
上海
|
3年以上
|
本科
|
全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2019-02-25发布

职位描述

Responsibilities:
•     Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
•     Develop infrastructure and environment for IP/SoC level design verification.
•     Closely working with Design/Architecture/Verification team to develop new verification component.

Requirements:
•     Major in Electrical Engineering, Computer Science or related
•     Good understanding on ASIC design verification flow
•     Good design verification experience
•     Programming knowledge on Verilog/SystemVerilog, C/C++
•     Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
•     Should have good communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
•     Strong problem solving skills