UVM验证

1.According to the design specification, be responsible for the verification plan and verification objective definition.
2.Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.
3.Work with Random Verification methodology(VMM, OVM, UVM, eRM)
4.Work as an independent verification engineers to check the design functionality at SOC module level and chip level.
5.Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.
6.Verilog or VHDL coding according to design specification or external/internal IP integration.
7.Support the post simulation with gate-level verilog or VHDL net list.
Requirements:
1.Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field， 2+ Years of verification working experience.
2.Experience with  Verification language (SPECMAN/E-language, System-Verilog, Vera)
3.Experience with RTL coding and simulators (Modelsim, NC-sim).
4.Basic knowledge of script language (Perl, TCL, C-language and so on)
5.Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.
6.Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.
7.Team oriented, love to work in young, international and highly motivated teams.
8.Good command of English