- 20万-40万/年
- 上海
- |
- 工作经验不限
- |
- 硕士
- |
- 全职
职位诱惑: 五险一金,福利好,老板nice,十五薪
发布时间: 2019-12-10发布
职位描述
Job Responsibility:
- Digital design of communication IC.
- Work with architect engineers to develop design specification of IP features
- RTL Implementation in Verilog HDL, CDC check, synthesis and timing analysis
- Work closely with verification and validation engineers to fix issues
Job Requirements:
- MS major in ME/EE/CS or related
- Experience with front-end IP/SoC design
- Skills in RTL Coding, synthesis, timing analysis and closure
- Knowledge of AMBA AXI/AHB/APB Bus
- Experience with USB/PCIe/SATA controller design is a plus
- Knowledge of FPGA development is a plus
- Strong script skill in Perl/Tcl is a plus
- Good english document reading and writing skills
- Good communication skill
- Quick learning skill
职位发布者
ASR HR
VP
7天
简历处理用时
100%
简历及时处理率
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