ASIC Digital Design egr(Timing, DFT Validation)

As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop timing constrain validation platform.

Position Responsibilities:
- Drive and work closely with RTL, implementation and methodology teams to establish a flow that brings the RTL and STA constraints into the in-house infrastructure for STA analysis
- Use the regression infrastructure to provide feedback to the RTL team on the timing-cleanliness of the design and the quality of the STA constraints themselves
- Participate in the discussions/reviews of the regression results to improve the correct and efficiency of the flow

Requirements:
Must have BSEE in EE with 5+ years of relevant experience or MSEE with 3+ years of relevant experience in the following areas:
- Demonstrates good communication skills in English
- Good skills in scripting and automation
- Experiences with timing/Synthesis constraints and floorplan-aware synthesis
- Knowledge of Verilog and IC design development cycle