- 40万-80万/年
- 青岛
- |
- 工作经验不限
- |
- 硕士
- |
- 全职
职位诱惑: 年终奖金,五险一金,福利好,老板nice,股票期权,技能培训,技术领先,成长空间大
发布时间: 2022-11-03发布
职位描述
- MSEE degree
- 5+ years of digital system design experience in CMOS processes
- Working knowledge of Verilog RTL language and high level modeling tools (Simulink, Matlab ...)
- Working knowledge of digital design flow from architecture, RTL design, verification, synthesis and timing analysis
- Strong lab and silicone validation skills
- Familiarity with FIR filter design is a strong plus
职位发布者
刘瑞伟
HR
7天
简历处理用时
100%
简历及时处理率
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