ASIC Design Verification Engineer

收藏职位

15万-30万/年
北京
|
应届生/在校生
|
本科
|
全职

职位诱惑: 五险一金,年终奖金,成长空间大,技术领先,免费班车,技能培训,交通补助,福利好,老板nice

发布时间: 2019-02-25发布

职位描述

Responsibilities:
•     Understand the ASIC design/verification flow and help design/verification engineers to accomplish targets.
•     Develop infrastructure and environment for IP/SoC level design verification.
•     Closely working with Design/Architecture/Verification team to develop new verification component.

Requirements:
•     Major in Electrical Engineering, Computer Science or related
•     Good understanding on ASIC design verification flow
•     Good design verification experience
•     Programming knowledge on Verilog/SystemVerilog, C/C++
•     Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
•     Should have good communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
•     Strong problem solving skills