ASIC Design Engineer（社招）

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15万-20万/年
上海
|
1-3年
|
硕士
|
全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,年底双薪,年度旅游,成长空间大,技术领先,节日礼物,技能培训

发布时间: 2017-11-23发布

职位描述

Job Requirement
1. Highly efficient in Verilog RTL coding
2. Hands-on experience on ASIC/FPGA design, verification flows, methodologies, network protocol Validation
3. Good understanding of modulator/demodulator design related techniques is a plus
4. Hands-on experience on Ethernet MAC/Switch/Network processing accelerator or 802.11 MAC ASIC/FPGA implementation and verification is a plus
6. Good document skills in english
7. Expertise in verification methodology such as systemVerilog/UVM is a plus and highly desired
8. Bachelor's or master's degree in semiconductor, electronic engineering or relevant speciality

Job Responsibilities
1 .Perform full cycle of IP development responsibilities, from circuit simulation, FPGA verification to chip validation.
2. communication IP/IC design, implementation and verification