Digital/ASIC Design Engineer (Front-end)
- 12万-20万/年
- 上海
- |
- 应届生/在校生
- |
- 硕士
- |
- 全职
职位诱惑: 年终奖金,五险一金,老板nice,股票期权,技术领先,成长空间大
发布时间: 2019-07-05发布
职位描述
Job Description:
1. This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
2. Work closely with analog/mixed-signal designers to build robust system-on-chip that is reliable under PVT variation.
3. Handle many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
4. Participate in chip debug, validation, and marketing specifications.
Qualifications:
1. Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, integration), timing analysis, DFT, meta-stability, etc.
2. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
3. Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
4. Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
5. Experience in common protocols, such as bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
6. Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
7. Experience in mixed-signal SOC design is a plus.
8. Experience in perl/python/tcl scripts is a plus.
职位发布者
Photonic HR
简历处理用时
简历及时处理率
光梓信息科技(上海)有限公司
领域: 通信网络
规模: 0-50人
主页: http://www.photonic-tech.com
工作地址:
上海市浦东新区亮秀路112号Y1座710(近金科路地铁站)
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