- 12万-24万/年
- 上海
- |
- 1-3年
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,五险一金,老板nice,股票期权,技术领先,成长空间大,十八薪
发布时间: 2019-07-05发布
职位描述
Responsibilities：
Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.
Qualifications:
1. BSEE, MSEE or higher.
2. 2~4 years experience of large ASIC backend designs.
3. Experience with Synopsys and/or Cadence design tools.
4. Familiar with 45/40nm or lower CMOS process designs.
5. Having successful tape out experience will be a great plus.
6. Good communication skills, team spirit and be anxious to learn during daily work.
职位发布者
Photonic HR
7天
简历处理用时
100%
简历及时处理率
光梓信息科技（上海）有限公司
领域: 通信网络
规模: 0-50人
主页: http://www.photonic-tech.com
工作地址:
浦东区亮秀路112号Y1楼710 （地铁2号线金科路站）
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