Design Verification Engineer(senior levels and above)

Design Verification Engineer(senior levels and above)
Job Overview:
Define testbench infrastructure using System Verilog, UVM and maybe Formal.
Assist in complete verification of high performance, high speed, low power ASIC.
Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure.
Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure.
Expert in wireline/wireless digital communication development.
Experienced in DSP or mix signal simulation is a big plus.
Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Responsibilities:
Responsibilities
Qualifications
Strong verification and technical lead skills including a good knowledge and understanding of different verification methodologies:
random vs directed testing
full chip vs module-level
performance vs function
error & drop handling
Past experience of successfully technically guiding complex, high speed design verification.

Experience with the following areas in design and verification:
Advanced constrained-random function verification methodology such as UVM/VMM and/or SV Assertion.
Digital communication systems/protocols such as 802.3, bluetooth, WiFi, 2G/3G/LTE.
High speed peripheral bus such as PCIE and USB.
Formal verification with abstraction model for end-to-end checking.
Self-motivated, good communicator, quick learner and good team player.
Display positive attitude and demonstrate flexibility in day-to-day work.