IC版图经理 Analog/RF Layout Design Engineer

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18万-36万/年
上海
|
5年以上
|
本科
|
全职

职位诱惑: 年终奖金,五险一金,老板nice,股票期权,技术领先,成长空间大,十八薪

发布时间: 2019-07-05发布

职位描述

Job Description:

- You will optimize the layout and high-frequency (multi-gigahertz) routing of high-precision analog circuits, such as:
high-speed amplifiers, wireline SERDES, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
- Use EDA tools (Cadence, Mentor, Allegro) to layout, extract, and verify the high-performance layout.
- Work and iterate with analog/RF design engineers to optimize the layout performance.

Qualifications:

- BSEE in analog IC design with 8+ years’ experience.
- Expert level experience in Cadence EDA tools.
- Team player with good communication skills.
- Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.
- Desired: Experience in RF circuit layout, including high-frequency effects, crosstalk, and bandwidth optimization.

- Desired: Experience in chip top level integration and verification.