Senior CAD Engineer(For Analog)

Responsibility
1. Be responsible for IC design flow developing, enhancing and supporting, including verification flow, IPDK (design kit) generation flow, physical design flow etc.;
2. Work with EDA vendor to develop and integrate new features in the overall design or verification flow;
3. Explore and support new flows and methodology to improve the design efficiency;
4. Be responsible to create useful scripts for IC design flow.

Requirements
Major in EE, CS or related, Master Degree with 1+ years or Bachelor with 3+ years working experiences
2+ years of IC design flow support experience.
Familiar with using Cadence design tools is a must.
Familiar with layout verification tools such as Hercules, Calibre is a must.
Familiar with design verification tools such as hsim, ncverilog, hspice etc. is a must.
Knowledge of layout Floorplan flow and place and route flow is a plus.
Understanding of basic CMOS circuits is a plus.
Good UNIX knowledge required. Programming experience required. UNIX, Shells, Perl, Skill, Python.
Good communication skills and be able to work both independently and in a team.