IC模拟版图

收藏职位

18万-30万/年
上海
|
5年以上
|
本科
|
全职

职位诱惑: 股票期权,技能培训,成长空间大

发布时间: 2019-07-05发布

职位描述

Job description:
- Individual will work closely with analog/mixed-signal engineers in the floor-plan, layout, and physical design of highly-integrated SoCs.

Qualifications:
- 5+ years experience with Cadence Virtuoso, Mentor Calibre, Synopsys.
- DRC, LVS, Metal Fill, Tapeouts, Metal Rules, Electromigration, Fringe Cap, Via rules, Matching, Inductance noise, wire resistance.
- Basic understanding of IC design (RLC circuits and Kirchoff’s Law, symmetry, frequency response, transistor matching).
- Desired: Analog layout design (differential symmetry; ground shielding; high-frequency impedances; current returns; noise coupling; transistor parasitics; parasitic fringe capacitances).